1. Field of the Invention
This disclosure relates to a semiconductor memory device and, more particularly, to a semiconductor memory device that can reduce the number of mode setting register codes used to set a test pattern data during a parallel bit test and a method of generating a test pattern data using the same.
2. Description of the Related Art
A conventional semiconductor memory device has to set and input different mode register setting codes (hereinafter, referred to as simply “MRS codes”) with respect to respective test patterns in order to write a test pattern during a parallel bit test. If the conventional semiconductor memory device is able to internally generate a total of 16 unique test patterns (a four-bit test pattern) in response to the MRS codes applied from an external tester during a parallel bit test, the external tester must provide 16 different MRS codes to generate the 16 unique test patterns during a parallel bit test.
Therefore, the conventional semiconductor memory device requires large numbers of MRS codes for a parallel bit test and thus MRS codes that could be put to other uses are in short supply.
Embodiments of the invention address these and other disadvantages of the conventional art.